LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
--USE ieee.std_logic_arith.all;
--USE ieee.std_logic_unsigned.ALL;

ENTITY regis IS
	PORT ( 	inp: IN INTEGER;
			store: IN STD_LOGIC;
			reg: OUT INTEGER);
END regis ;

ARCHITECTURE regis OF regis IS
BEGIN
	regis: PROCESS (inp,store)
	BEGIN	
		-- reset the counter
		if store = '0' then
			reg <= inp;
		end if;
	END PROCESS;
END regis ;
